Architecture related Types and Helpers.
This module defines the types and helpers functions to properly handle architecture specific components
Classes | |
| struct | eve::fundamental_width< Type, ABI > |
| Computes the fundamental width of a given type. More... | |
| struct | eve::platform |
| Platform specific constexpr information. More... | |
Typedefs | |
| template<typename Type, regular_abi ABI = eve::current_abi_type> | |
| using | eve::expected_width_t = lanes_t<expected_width_v<Type,ABI>> |
| Computes the expected width of a given type. | |
Variables | |
| template<scalar_value T, regular_abi ABI = eve::current_abi_type> | |
| constexpr width_type | eve::nofs_width_v |
| nofs stands for "no frequency scaling". | |
| using eve::expected_width_t = lanes_t<expected_width_v<Type,ABI>> |
Computes the expected width of a given type.
Required header: #include <eve/arch/expected_width.hpp>
eve::expected_width_t is the exact width type of the register able to store values of type Type for a given SIMD ABI as a native register type.
| Type | Type of value to assess |
| ABI | SIMD ABI to use as reference. Must models eve::regular_abi. |
|
constexpr |
nofs stands for "no frequency scaling".
You can find more explanations in the 'frequency scaling tutorial'. This refers to extreme frequency scaling one encounters when working with 64 byte registers on intel. The processor scales frequency drammatically for a substantial period of time. So even if the algorithm itself will run faster the overall perf will go down. Generally speaking, 64 byte registers on intel make sense only for really big data sets. nofs_width will produce 32 byte registers on avx512. If you would like to default to 64 byte registers, you can build with DEVE_AVX512_DEFAULT_64_BYTES. This is probably a good idea on AMD-ZEN4 but we do not detect that at the moment.
| Type | Type of value to assess |
| ABI | SIMD ABI to use as reference. Must models eve::regular_abi. defaults to current. |